JPS647507B2 - - Google Patents

Info

Publication number
JPS647507B2
JPS647507B2 JP21178283A JP21178283A JPS647507B2 JP S647507 B2 JPS647507 B2 JP S647507B2 JP 21178283 A JP21178283 A JP 21178283A JP 21178283 A JP21178283 A JP 21178283A JP S647507 B2 JPS647507 B2 JP S647507B2
Authority
JP
Japan
Prior art keywords
circuit
logic integrated
scan path
circuit section
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP21178283A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60103638A (ja
Inventor
Masakazu Kaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP21178283A priority Critical patent/JPS60103638A/ja
Publication of JPS60103638A publication Critical patent/JPS60103638A/ja
Publication of JPS647507B2 publication Critical patent/JPS647507B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP21178283A 1983-11-11 1983-11-11 半導体論理集積装置 Granted JPS60103638A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21178283A JPS60103638A (ja) 1983-11-11 1983-11-11 半導体論理集積装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21178283A JPS60103638A (ja) 1983-11-11 1983-11-11 半導体論理集積装置

Publications (2)

Publication Number Publication Date
JPS60103638A JPS60103638A (ja) 1985-06-07
JPS647507B2 true JPS647507B2 (en]) 1989-02-09

Family

ID=16611506

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21178283A Granted JPS60103638A (ja) 1983-11-11 1983-11-11 半導体論理集積装置

Country Status (1)

Country Link
JP (1) JPS60103638A (en])

Also Published As

Publication number Publication date
JPS60103638A (ja) 1985-06-07

Similar Documents

Publication Publication Date Title
US4635261A (en) On chip test system for configurable gate arrays
US4293919A (en) Level sensitive scan design (LSSD) system
US4051352A (en) Level sensitive embedded array logic system
EP0388001A2 (en) Testing method and apparatus for an integrated circuit
US20030169070A1 (en) Method and apparatus for built-in self-test of logic circuits with multiple clock domains
JPH06208602A (ja) 可検査性設計規則の検証方法
JPH0697244A (ja) 集積回路チップの相互接続検査方法
JPH0572290A (ja) 半導体集積回路
EP0499671A1 (en) Integrated circuit chip with built-in self-test for logic fault detection
US7613969B2 (en) Method and system for clock skew independent scan register chains
JPS6134174B2 (en])
US5802075A (en) Distributed test pattern generation
GB2041546A (en) Logic module or logic means for or in an integrated digital circuit
US6275081B1 (en) Gated clock flip-flops
US6237117B1 (en) Method for testing circuit design using exhaustive test vector sequence
US6810498B2 (en) RAM functional test facilitation circuit with reduced scale
JPH10133768A (ja) クロックシステム、半導体装置、半導体装置のテスト方法、及びcad装置
US5726998A (en) Partial scan path test of a semiconductor logic circuit
JPS647507B2 (en])
US6530051B1 (en) Method and apparatus for an easy identification of a state of a DRAM generator controller
JP3291706B2 (ja) 論理回路の高速動作検証方法、及び、論理回路
JP3695768B2 (ja) テスト回路の検証方法
JPS59211146A (ja) スキヤンイン方法
JPH0440736B2 (en])
JPH06148293A (ja) 論理回路テスト回路